A varying electrical signal produces electromagnetic radiation (EMR), which may interfere with radio frequency (RF) signals. Electronic devices often contain one or more RF components comprising receivers, transmitters or transceivers for wireless communication as well as one or more components that require a periodic clock signal, referred to as clocked components, to operate. The one or more clock signals may be generated by a voltage controlled oscillator (VCO) or a phase lock loop (PLL) and a crystal oscillator. The crystal oscillator provides a base clock signal of a fundamental frequency, which may be multiplied and/or divided to generate the required frequency of the clock signal. The frequency of the clock signal provided by a VCO may be adjusted by the voltage applied to the VCO.
The clock signal or signals required by one or more clocked components of the electronic device may cause undesirable radio frequency interference (RFI) with the RF components of the electronic device depending on the frequency of the clock signal(s) and a channel frequency of the RF component being used. In order to reduce the clock generated RFI, the RF component may be provided with shielding to reduce the effects of the RFI. However, the RFI may still interfere with the desired signal at unshielded points of the RF component, such as at an antenna.
Previous attempts at reducing clock-generated RFI included spreading the frequency spectrum of the clock signal by introducing clock jitter, which varies the clock frequency slightly above and below the desired clock frequency. However, introducing clock jitter may be unsuitable for clocked components that require a precise clock signal, such as a display component.
A further attempt, described in U.S. Published Patent Application US 2009/0138745 A1, published May 28, 2009, included determining the RF frequencies used by the RF components of the electronic device and creating a list of safe fundamental clock signal frequencies. The clock signal frequencies of the device could then be adjusted based on the list of safe frequencies to avoid collisions between harmonics of the adjusted clock signal frequencies and the RF frequencies of the RF components. While this could reduce the collisions, the deterministic nature of the safe list of fundamental clock frequencies did not adjust to varying factors that could affect the clock generated RFI. Furthermore, the previous attempts required that the PLL (phase locked loop) or VCO (voltage controlled oscillator) actually produce the clock signal at the desired frequency selected from the safe list of frequencies. However, such a requirement may be difficult to meet, due to variations in the manufacture of the clock source and/or the environment of the clock source and/or the aging of the clock source.